1. Field of the Invention
This invention relates generally to a video signal recording and/or reproducing system for recording and/or reproducing a video signal with high quality, and specifically to a video-signal-system converting circuit for processing a video signal having interlaced scanning lines to produce a video signal having sequential scanning lines. The present invention also relates to a video signal subsampling circuit for offset-sampling a line sequential video signal within a frame to compress the amount of data as well as to a video signal interpolating circuit for interpolating the compressed video signal to recover the original video signal.
2. Prior Art
As large-screen television sets have become more common, visual characteristics such as flicker and blur of a picture have become noticeable. In order to solve a growing demand for improvement of picture quality, various high quality-picture television systems has been developed. Such television systems include the IDTV(Improved Definition Television) system, the EDTV(Extended Definition Television) and the HDTV(High Definition Television) system. The IDTV is intended to improve the vertical resolution of a picture through the use of sequential line scanning without the need for the improvement or change of existing systems. The EDTV system is intended to improve the vertical and horizontal resolutions by making necessary improvement in and modification to the existing system while maintaining the compatibility of the new system with the existing systems. The HDTV is completely independent of existing television systems, is an ideal television system for the next generation. Some of the new television systems have been put into practical use in the television broadcasting. Meanwhile, the NTSC system is still the only system being used in the package media such as a VTR and a VDP. The package media, particularly consumer package media, are behind the broadcasting in terms of improvement in picture quality.
One of the technologies for improving picture-quality is a conversion technique for converting interlaced scanning lines into progressive scanning lines. One such conversion technique is the intra-field/inter-field interpolation technique suitable for frequently moving pictures. This interpolation consists of the intra-field interpolation where the data of the preceding field are simply delayed so as to use the data as new scanning lines, and the inter-field interpolation where a new scanning line is produced by averaging the data of adjacent upper and lower scanning lines. With this type of interpolation, while a satisfactory picture can be obtained for a still picture, cross talk occurs to adversely affect picture quality when there is no correlation in moving a picture between fields, and a variation in vertical resolution occurs when a picture starts to slowly move and then stops. This is probably due to the fact that the moving portion of the picture is interpolated by averaging.
FIG. 15 shows one such conventional video signal subsampling circuit. Referring to FIG. 15, the subsampling circuit is adapted to offset sample (quincunx sampling) a video signal having sequential scanning lines within a frame so as to compress the amount of data of the video signal. In the figure, progressive scanning lines are inputted to an input terminal 510. A line memory 511 stores therein data of a length of "one line minus one picture element". A first and a second delay circuit 512 and 513 each store therein one picture element outputted from the line memory 511. A line memory 514 stores therein data of a length of "one line minus one picture element". A multiplying circuit 515 receives the signal from the input terminal and outputs a signal multiplied by a coefficient K3. The output of the memory 511 and the output of the delay circuit 513 are supplied to an adder 516 which outputs the sum of the two signals supplied thereto. A multiplying circuit 517 receives the signal from the adder 516 and outputs a signal multiplied by a coefficient K2. A multiplying circuit 518 receives the signal from the delay circuit 512 and outputs a signal multiplied by a coefficient K1. A multiplier 519 receives the output of the line memory 514 and outputs a signal multiplied by a coefficient K3. An adder 520 adds the outputs of the multipliers 515 and 517-519 and supplies the sum to a switch 521. The switch 520 is switched between a position a and a position b to selectively pass the output of the adder 520 and "zero" (i.e., ground) at a clock frequency of fs. The output of the switch 521 is supplied directly to a position a of a switch 523 and via a delay circuit 522 to a position b. The switch circuit 523 is switched between the positions a and b for every line(H) so as to output the thus subsampled video signal.
Progressive scanning lines as shown in FIG. 16a are inputted to the input terminal 10 in the order of L1 (picture elements P10, P11, . . . ), L2(P20, P21, . . . ), L3(picture elements P30, P31, . . . ), . . . etc. The video lines of "3 elements by 3 lines" are multiplied by coefficients K1-K4 in the form of a 3 by 3 matrix as shown in FIG. 16b, so that the picture element data are subsampled to produce a compressed-picture-element data on the basis of an element and its adjacent elements. Such data processing is effected line by line for every other elements in a line. For example, a compressed element P21' is calculated from picture elements of 3 by 3 (i.e., nine elements) P10-P12, P20-P22, and P30-P32 as follows: EQU P21'=K1P21+K2(P20+P22)+K3(P11+P31)+K4(P10+P12+P30+P32)
Since the picture elements P22, P21, P20, and P11 are outputted from the line memory 511, delay circuits 512 and 513, and line memory 514, the picture element P21' is given by the following expression. EQU P21'=K1P21+K2(P20+P22)+K3(P11+P31)
In this manner, the video signal having progressive scanning lines are subjected to quincunx sampling within a frame, so that a total of five picture elements, four of which are aligned to diagonally surround a center element, are multiplied by a group of coefficients in the form of 3 by 3 matrix to produce a compressed picture element corresponding to the center element.
At the next clock, the switch 521 makes contact with terminal a, which is grounded its, so that the output data subsequent to P21' is zero as shown in FIG. 16c.
Then, the picture element data from the switch 521 are shifted one element to the left by the delay circuit so that they are aligned in vertical lines or columns as seen in FIG. 16d.
When demodulating the thus compressed video signal as shown in FIG. 17a, the data "zeros" are inserted between adjacent elements of the compressed data as shown in FIG. 17b such that a zero appears every other element in each line and between the zeros in the previous line. The data are then multiplied by coefficients in the form of a 3 by 3 matrix. FIG. 17c shows the calculation of a data matrix (P12', P21', P32' and P23') times a coefficient matrix (J1-J4) to produce a picture element data P22. Likewise, calculation is carried out for the data in respective lines. The coefficients J1-J4 are in a relation of Jn=2Kn. The above described conventional sampling and interpolating process is disadvantageous in that not only the respective circuits are required of high speed operation but also the memories for storing a length of picture element data must have a large storage capacity since the associated circuits must be operated with a sampling frequency of fs.